1. Field of the Invention
The present invention relates generally to semiconductor memory devices and more particularly to semiconductor memory devices that allow multiple bits per cell.
2. Background of the Invention
Band-to-band (BTB) PHINES memory cells are a type of memory cell that can store 2 bits per cell. One bit can be stored on the source side of the transistor and one bit can be stored on the drain side of the transistor. In these memory cells each bit can have two states; a high current state that can represent a logic “1” and a low current state that can represent a logic “0”. Each side of the memory cell can be read by sensing the current through the cell and determining if the current is higher or lower than a threshold. Programming and reading BTB-PHINES memory cells will be discussed further with respect to FIG. 1A, which is a diagram illustrating an example BTB-PHINES memory cell 100, and FIG. 1B, which illustrates the sensing current for an erased and programmed cell.
Transistor 100 includes a silicon substrate 102 that is the base material that the rest of the memory device can be fabricated from. Two n+ regions 104 and 106 can be created by doping the silicon substrate. These regions 104 and 106 can act as source and drain for transistor 100. An ONO layer 108 can then be deposited on top of silicon substrate 102 between n+ regions 104 and 106 and a polysilicon layer (not shown) can be deposited on top of ONO layer 108 to form the gate of transistor 100. ONO layer 108 can include a nitride (n) layer 110 that traps charge, sandwiched between two silicon oxide layers.
Transistor 100 can be configured to store data. Data can be stored by “programming” and “erasing” a memory cell comprising transistor 100. In the erased state, a low number of “holes”, i.e., less holes than electrons, are in nitride layer 110. When a low number of holes are present in nitride layer 110 more current flows through the transistor, e.g., from substrate to source or substrate to drain.
Programming of the memory cell is achieved by hot hole injection into nitride layer 110. As holes are injected into nitride layer 110 fewer and fewer electrons reside in layer 110. As fewer electrons remain in layer 110 less negative charge exists in layer 110. For this reason layer 110 exhibits more positive charge as more holes are injected into nitride layer 110. As nitride layer 110 becomes more and more positively charged it takes more negative voltage on the gate to get a given amount of current to flow. For this reason, as more holes are injected into nitride layer 110 less current flows for a given gate and drain or gate and source voltage. During program operation, holes are injected to compensate for, or recombine with, the stored electrons. Electrons and holes coexist in the memory cell. In the programmed state, the number of holes is more than the number of electrons. In the erased state, the number of electrons is more than the number of holes.
As described above, the BTB current of an erased cell is higher than the BTB current of a programmed cell. For this reason the state of each side of each cell, programmed or not programmed, can be determined by comparing the current through each side of each cell to a threshold, e.g., a substrate to drain or substrate to source current threshold.
In a PHINES memory device the charge accumulated on nitride layer 110 can be erased by a process known as Fowler-Nordheim Injection. During an erase cycle, erase voltages are applied to the source, drain, gate and body of transistor 100 that cause electrons to tunnel through the bottom or top oxide barrier of ONO layer 110 into the nitride layer. These electrons can compensate for the holes injected into nitride 110 layer during programming. The tunneling through the bottom or top oxide layer can occur in the presence of a high electric field, created as a result of application of the erase voltages to transistor 100, and is a form of quantum mechanical tunneling.
FIG. 1B is a graph illustrating the read operation of cell 100. As can be seen, during a read, a read voltage of 2 volts can be applied to source 106, while a −10 volt read voltage is applied to the gate and drain 104 is allowed to float. The resulting source current can then be monitored in order to determine whether cell 100 is programmed. If the cell is programmed, then the current will be low as illustrated in FIG. 1B. If, on the other hand, the cell is erased, then the current will be relatively high as illustrated in FIG. 1B The other side of cell 100 can be read by switching the drain and source voltages and monitoring the drain current.
Storing two bits per cell can increase memory density, however, application and data needs for electronic devices continues to grow, which continues to drive requirements for even greater densities than provided by conventional memory devices.